Oxygen Precipitation Kinetics and Internal Gettering (IG) in CZ Silicon Wafers for High-Yield CMOS Image Sensors

High-performance CMOS Image Sensors (CIS) utilized in mobile devices, automotive vision systems, and industrial inspection demand ultra-low dark current, zero white spot defects, and high quantum efficiency. Because photodiode pixel arrays are fabricated directly within the top few micrometers of the silicon substrate, any metallic impurity—such as trace iron, copper, or nickel—can create deep-level traps in the bandgap. These traps accelerate thermal generation of electron-hole pairs, leading to unacceptable dark current spikes and fixed-pattern pixel noise.

To eliminate metallic contamination from active pixel regions, semiconductor foundries rely on Internal Gettering (IG). Internal Gettering takes advantage of oxygen precipitation kinetics inherent to Czochralski (CZ) grown silicon. By subjecting the substrate to precise thermal annealing sequences, dissolved interstitial oxygen precipitates into silicon oxide clusters within the bulk wafer. These clusters form dislocation loops and Bulk Micro-Defects (BMD) that act as permanent trapping sinks for metallic impurities. Crucially, the surface region where photodiodes reside is cleared of oxygen, forming a defect-free Denuded Zone (DZ).

Achieving high-yield CIS manufacturing requires tight control over oxygen nucleation, furnace temperature profiling, and substrate selection. Process engineers rely on specialized material configurations to calibrate and execute these steps. For instance, evaluating annealing profiles requires an economical Test Wafer, controlling surface out-diffusion and masking demands a thermal Oxide Wafer, and device fabrication depends on a defect-engineered Prime Wafer. At FSM, we deliver precision silicon substrate solutions tailored for demanding image sensor workflows.

Physics of Oxygen Precipitation Kinetics and Internal Gettering (IG)

Czochralski (CZ) silicon wafers naturally contain dissolved interstitial oxygen introduced from quartz crucible dissolution during crystal growth. When heated, this supersaturated interstitial oxygen precipitates into silicon dioxide (SiO2) micro-complexes according to thermodynamic and kinetic parameters governed by temperature, initial oxygen concentration [Oi], and crystal thermal history.

The formation of an effective Internal Gettering structure in CZ silicon is achieved through a classical three-step thermal annealing cycle:

1.High-Temperature Out-Diffusion Step (1100℃to 1150℃)

During the initial high-temperature step, interstitial oxygen rapidly diffuses out of the wafer surface into the ambient environment. This creates a steep oxygen concentration gradient from the surface into the bulk. Near the surface, the oxygen concentration drops below the solubility limit, establishing a pristine, precipitate-free Denuded Zone (DZ) typically 10 to 30 micrometers deep.

2.Low-Temperature Nucleation Step (650℃to 800℃)

In the second step, the wafer is cooled to a lower temperature regime where interstitial oxygen supersaturation is extremely high. Oxygen atoms aggregate around point defects (vacancies and interstitials) to form critical SiO2 precipitate nuclei throughout the bulk silicon, while the surface DZ remains free of nucleation due to low local oxygen concentration.

3.High-Temperature Precipitate Growth Step (1000℃to 1050℃)

The final high-temperature annealing step accelerates the growth of oxide nuclei into macroscopic Bulk Micro-Defects (BMD). As SiO2 precipitates expand, they induce localized lattice strain and generate secondary dislocation loops. These bulk defects create high-energy lattice sites that aggressively capture fast-diffusing transition metals (Fe, Cu, Ni) during subsequent thermal processing, effectively gettering impurities away from the frontside photodiodes.

Substrate Optimization and FSM Substrate Solutions

Successfully executing Internal Gettering requires balancing initial interstitial oxygen levels, thermal budgets, and surface protection layers. FSM provides engineered wafer solutions specifically matched to every phase of CIS substrate preparation and IG process qualification.

FSM Prime Wafer Solutions for Image Sensor Active Layers

For final device manufacturing, the substrate must feature precise initial oxygen concentrations [Oi] (typically between 22 to 30 ppma depending on the gettering strategy) combined with ultra-low Crystal-Originated Particle (COP) counts.

FSM supplies high-purity Prime Wafer products engineered for advanced sensor applications:

Controlled Interstitial Oxygen [Oi]: Customized oxygen concentration range and tight radial distribution to guarantee consistent BMD density across 200 mm and 300 mm substrates.

Superior Surface Topography: Double-Side Polished (DSP) and Single-Side Polished (SSP) options featuring surface roughness Ra < 0.1 nm, preventing surface micro-roughness from scattering incident light in backside-illuminated (BSI) CIS architectures.

Low Defect Density: Minimized vacancy-type defects to ensure that the Denuded Zone (DZ) remains completely free of mechanical or structural flaws.

FSM Test Wafer Line for IG Thermal Profile Calibration

Establishing three-step annealing recipes requires extensive thermal modeling and destructive defect characterization. Utilizing prime production substrates for furnace qualification, FTIR oxygen mapping, and cross-sectional cleavage analysis introduces unnecessary costs.

FSM provides dedicated Test Wafer inventory across 2-inch to 12-inch diameter formats:

Process Qualification: Ideal for calibrating high-temperature out-diffusion furnaces, determining BMD nucleation rates, and mapping radial DZ uniformity.

Cost-Effective Metrology: Enables process engineers to verify gettering efficiency and optimize thermal recipes without consuming high-value active device inventory.

FSM Oxide Wafer Products for Surface Protection and Masking

During high-temperature oxygen out-diffusion and precipitation growth steps, protecting the polished silicon surface from thermal pitting, chemical contamination, and un-controlled oxidation is critical.

FSM offers thermal Oxide Wafer products across 200 mm and 300 mm specifications:

Thermal SiO2 Capping: High-purity thermally grown oxide layers act as protective caps during out-diffusion annealing, maintaining surface smoothness and preventing external impurity in-diffusion.

Uniform Masking: Exceptional oxide thickness uniformity across the substrate ensures consistent thermal transfer and predictable oxygen out-diffusion kinetics.

Metrology and Gettering Efficiency Verification

To verify that oxygen precipitation kinetics have yielded an optimal Internal Gettering structure, semiconductor quality control laboratories utilize both non-destructive and destructive analytical techniques:

Fourier Transform Infrared Spectroscopy (FT-IR): Quantifies the drop in interstitial oxygen concentration [Oi] before and after annealing. The reduction in interstitial oxygen directly correlates with the volume of precipitating SiO2 in the bulk.

Cleavage and Selective Chemical Etching: Wafers are cleaved and subjected to preferential etching (e.g., Wright or Secco etch). Optical microscopy or Scanning Electron Microscopy (SEM) is then used to measure the physical depth of the Denuded Zone (DZ) and count Bulk Micro-Defect (BMD) density (typically targeting 1E9 to 1E10 defects/cm³).

Infrared Tomography (IRT): Non-destructive laser scattering method used to inspect BMD distribution inside bulk silicon.

In a typical foundry qualification workflow, engineers rely on a Test Wafer to tune thermal ramp rates, verify furnace cleanliness using an Oxide Wafer protective cap, and subsequently run active production on an optimized Prime Wafer to achieve zero-defect pixel arrays.

Conclusion: Partnering with FSM for High-Yield CIS Substrates

Controlling oxygen precipitation kinetics and Internal Gettering is fundamental to eliminating dark current defects in next-generation CMOS Image Sensors. Achieving high manufacturing yields requires an integrated approach that couples precise thermal annealing with tightly specified CZ silicon substrates.

FSM supports global semiconductor manufacturers, sensor foundries, and research institutions with specialized substrate solutions tailored for image sensor development:

High-purity Prime Wafer substrates with customized oxygen ranges for low-noise sensor active layers.

Economical Test Wafer options for thermal annealing optimization, BMD density testing, and DZ depth verification.

Thermally grown Oxide Wafer products for high-temperature surface protection and process masking.

To discuss custom oxygen specifications, thermal history requirements, or bulk substrate sourcing for your CIS production line, visit FSM Wafer Solutions.